1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor that includes a plurality of capacitor units in a unitary structure and has a low equivalent series inductance (ESL) and a high series resistance (ESR) which can be controlled within the broadband frequency range, a circuit board apparatus having the multilayer chip capacitor, and a circuit board for mounting the multilayer chip capacitor.
2. Description of the Related Art
A multilayer chip capacitor has been widely used as a decoupling capacitor for the stabilization of power circuits such as a power distribution network of a micro processing unit (MPU). The multilayer chip capacitor used for the decoupling purpose functions to suppress voltage noise by supplying an electric current to CPU chips when the applied current are changed rapidly.
In general, the MPU is continuously increased in current consumption and decreased in operation voltage as its integration density increases. Also, its operation speed is continuously increased. Accordingly, it is increasingly difficult to suppress noise of a supply DC voltage within a certain range since the noise is generated by the sudden change in the consumed current of the MPU. Recently, an applied current is changed more rapidly with the increase in an operating frequency of the MPU. Therefore there is required a multilayer chip capacitor capable of increasing the capacitance and ESR of a decoupling capacitor and decreasing ESL of the decoupling capacitor. This is merely designed to maintain impedance of a power distribution network to a constant level within the broadband frequency range, and ultimately prevent noise of the supply DC voltage by the sudden change of the applied current.
In order to meet low ESL characteristics required for the decoupling capacitor used in the MPU power distribution network, there have been proposed methods of modifying the position, form or shape of the external and internal electrodes in a capacitor. For example, U.S. Pat. No. 5,880,925 proposes a plan to reduce ESL by disposing leads of first and second internal electrodes of different polarities in an interdigitated arrangement, while the first internal electrodes and the second internal electrodes are adjacent to each other, thereby to form current paths in the capacitor effectively. This prior-art method leads to a decrease in ESL but may, disadvantageously, entail a reduction in ESR besides the ESL. Stability of the power circuit depends on the ERS as well as the ESL of the capacitor. Therefore, the power circuit becomes unstable when the ESR is too low, and the voltage may be changed suddenly due to power network resonance. Accordingly, the capacitor as described in the US patent is effective to reduce high frequency impedance, but hardly maintains the impedance of the power distribution network to a constant level due to very low ESR.
In order to solve the problem associated with very low ESR, there has been proposed a plan for realizing high ESR characteristics using electrically high-resistant materials in the external electrodes and internal electrodes. However, the use of the high-resistant external electrodes has some difficulty in preventing localized heat spots caused by current channeling phenomenon through pinholes in the external electrodes, which also makes it difficult to control ESR precisely. Also, when the high-resistance materials are used in the internal electrodes, the problem is that high-resistant internal electrode materials should be changed with the improvement or changes of ceramic materials since the high-resistant internal electrode materials should be matched with ceramic materials, which leads to the increased cost of the products.
US Patent Publication No. 2006/0209492 proposes a capacitor having low impedance in a wide frequency band by integrally disposing two capacitors of different capacitances in the same capacitor body. However, the capacitor does not maintain the power network impedance to a constant level (in the vicinity of each resonance frequency), as described in the patent publication, and therefore the constant impedance of the power network adversely affects the stability of a power circuit.